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Development of model
examples
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implementation of models in VHDL-AMS
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exchange of models including test bench
and documentation
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exchange of experiences concerning
simulation results
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of different tools (stability,
computation time etc.)
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Evaluation of tools for converting SPICE,
MAST, … to VHDL-AMS
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Definition of a subset of VHDL-AMS for
Real-time applications
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(VHDL-AMS-RT) to model plants tool
independently
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Cooperation with tool developer (Avant!,
ETAS, Mathworks,
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Mentor Graphics, …)
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Building of an MSR library and package
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